1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, particularly, a semiconductor device having an insulated gate bipolar transistor (IGBT) and a method of manufacturing the same.
2. Description of the Related Art
An insulated gate bipolar transistor is called IGBT, in which a fundamental cell combines the bipolar transistor and the MOS transistor, forming a semiconductor device having both low on-voltage characteristics of the former and voltage drive characteristics of the latter.
FIG. 10 shows a conventional semiconductor device, more specifically, a cross-sectional view of a punch-through type IGBT. This cross-sectional view shows one unit cell only, but a number of unit cells are connected in parallel actually.
First, the structure of the conventional semiconductor device will be described. An n+-type buffer layer 102 and an n−-type drift layer 103 are formed on the front surface side of a p++-type semiconductor substrate (a collector layer 101) by epitaxial growth. P-type base regions 104 are selectively formed in the front surface of the drift layer 103, and n+-type emitter regions 105 are selectively formed in the front surface of the base regions 104. Gate electrodes 107 are further formed covering the front surfaces of the base regions 104 at least in regions between the emitter regions 105 and the drift layer 103, with gate oxide films 106 interposed therebetween. Furthermore, the gate electrodes 107 are surrounded by an insulation film 108, and an emitter electrode 109 is formed covering the insulation film 108 and being connected with the emitter regions 105. On the other hand, a collector electrode 110 is formed on the back surface side of the collector layer 101. The gate electrodes 107, the emitter electrode 109 and the collector electrode 110 are electrically connected among all the unit cells, respectively.
Next, the operation of the conventional semiconductor device will be described. When a gate voltage over a threshold is applied between the emitter electrode 109 and the gate electrodes 107 in the state where a collector voltage is applied between the emitter electrode 109 and the collector electrode 110, channel regions in the base regions 104 adjacent to the gate electrodes 107 are inverted into the n-type. Then, electrons are injected from the emitter electrode 109 to the drift layer 103 through the channel regions.
With these electrons, the collector layer 101 and the drift layer 103 are forward biased, and holes are injected from the collector layer 101 to the drift layer 103. As a result of this, the resistance of the drift layer 103 is largely reduced, and a collector current flowing from the collector electrode 110 to the emitter electrode 109 reaches a high value.
The buffer layer 102 also has a function of preventing punch-through. In detail, without the buffer layer 102, a depletion layer expanding from the base regions 104 reaches the collector layer 101 when a collector voltage exceeds a breakdown voltage, and thus a collector current inadvertently flows even when a gate voltage is not applied. In this respect, when the buffer layer 102 is provided, the expansion of the depletion layer slows down in the buffer layer 102 and is prevented from reaching the collector layer 101. This realizes a higher breakdown voltage even with the thinner collector layer 101, and the turn-off loss is also minimized.
Furthermore, the buffer layer 102 has a function of minimizing the amount of the holes injected from the collector layer 101. That is, the buffer layer 102 has a high concentration of n-type impurity, and the holes injected from the collector layer 101 are easily recombined with the electrons in the buffer layer 102. Therefore, the on-resistance and the collector current are adjusted with the thickness and the impurity concentration of the buffer layer 102. The relevant technology is described in the Japanese Patent Application Publication No. 2001-160559, for example.
The IGBT is used as a switching element in an inverter circuit for driving a load such as a motor. FIG. 11 shows a circuit diagram of an inverter circuit for driving a motor.
For example, when the IGBTa and the IGBTd turn on and a direct current voltage is applied to a motor load M, a current flows while accumulating and increasing an energy in the motor load M. After that, when the IGBTa and the IGBTd turn off, a current is discharged from the motor load M. At this time, if the energy accumulated in the motor load M is discharged for an instant, this current is extremely large and thus the IGBTs are broken.
For solving this, in the inverter circuit, a free wheeling diode (hereafter, referred to as FWD) is reversely and in parallel connected to each of the IGBTs. Therefore, when the IGBTa and the IGBTd turn off, a current flows back from the motor load M, taking a detour through the FWDb and the FWDc reversely and in parallel connected to the IGBTb and the IGBTc. In detail, even when the IGBTa and the IGBTd turn off, a current flowing in the motor load M is not blocked suddenly, so that the energy accumulated in the motor load M is slowly discharged and the IGBTs are not broken.
Accordingly, it is necessary in the inverter circuit to connect the FWD to each of the IGBTs reversely and in parallel. However, in the IGBT, the p++-type collector layer 101 is formed on the whole back surface. This means the FWD is not integrated in the IGBT structurally, but a forward diode including the p++-type collector layer 101 and the n+-type buffer layer 102 is rather integrated therein.
Therefore, in the inverter circuit, the IGBT and the FWD need be configured of separate elements, and these elements are reversely and in parallel connected on a substrate in a package. This causes a large number of processes and components and a difficulty in reducing the cost.